The invention relates to transistor circuits, and more particularly to transistor circuits with a terminal receiving predetermined high voltages and electrical signals.
A typical conventional transistor circuitry with the terminal for receiving both the high voltage and the electrical signals will be described with reference to FIG. 1. The transistor circuitry has an input terminal 1 for receiving both the high voltage and the electrical signals, a signal output terminal 5 from which electrical signals are outputted and a high voltage output terminal 3 from which a high voltage is outputted. The transistor circuitry also has an input circuit 2 that is electrically connected in series between the input terminal 1 and the signal output terminal 5 for receiving the electrical signals from the input terminal 1 and subsequent supply of the output signals to the signal output terminal 5. The transistor circuitry further has an n-channel transistor 6 that is electrically connected between the input terminal 1 and the high voltage output terminal 3. The n-channel transistor 6 has a gate to which a control signal is applied, according to which the transistor 6 exhibits switching operations. The n-channel transistor has a substrate that is grounded.
Operations of the conventional transistor circuitry will subsequently be described. The n-channel transistor 6 serves as a switch. When the input terminal 1 receives a high voltage, the control signal is at a high level and is applied to the gate electrode 4 to have the switching transistor 6 turn on so that the high voltage that has been received by the input terminal 1 is transmitted through the switching transistor 6 to the high voltage output terminal 3. By contrast, when the input terminal 1 receives electrical signals, the control signal is at a low level and is applied to the gate electrode 4 to have the switching transistor 6 turn off so that the electrical signals are supplied into the input circuit 2 and subsequently output from the signal output terminal 5.
The above described conventional transistor circuitry has a serious problem as described below. The above circuitry requires that the n-channel switching transistor be designed to have a considerable large channel width for an appreciable reduction of a voltage drop caused by the switching transistor. The large channel width of the switching transistor 6 necessitates a large occupation area of the switching transistor. This provides a difficulty in achieving a high density integration of the transistor circuits. The above circuitry further requires a booster such as a charge pump that generates a high control voltage to be applied to the gate electrode of the switching transistor 6, although an illustration of the booster or the charge pump is omitted. The booster or the charge pump also occupies a large area. This also provides a difficulty in achieving a high density integration of the transistor circuits.
To combat the above problem, another conventional transistor circuitry has been proposed, descriptions of which will be made with reference to FIG. 2A. This conventional transistor circuitry has an input terminal 10 for receiving a high voltage and electrical signals, a signal output terminal 12 from which electrical signals are outputted and a high voltage output terminal 14 from which a high voltage is outputted, in addition a power source voltage terminal 16 to which a power source voltage is applied. This conventional transistor circuitry has an input circuit 11 that is electrically connected in series between the input terminal 10 and the signal output terminal 12 for receiving the electrical signals from the input terminal 10 and for the subsequent supply of output signals to the signal output terminal 12. The transistor circuitry further has first and second n-channel transistors 21 and 22, both of which are electrically connected in series between the input terminal 10 and the power source voltage terminal 16. The transistor circuitry also has a charge pump 18 that is connected to a gate of the first n-channel transistor 21 for supplying a high voltage control signal S21 to the gate of the first n-channel transistor 21. The first n-channel transistor 21 has a source electrically connected to the input terminal 10 and a source electrically connected to an intersection 20, while the second n-channel transistor 22 has a gate receiving a control signal S22, a drain that is electrically connected to the intersection 20 and a source that is electrically connected to the power source voltage terminal 16. The power source voltage terminal 16 is applied with a power source voltage V.sub.dd. The first and second n-channel transistors 21 and 22 have substrates that are grounded to provide a ground potential to the substrate. The transistor circuitry also has a third p-channel transistor 23 that is electrically connected in series between the input terminal 10 and the high voltage output terminal 14. The third p-channel transistor has a gate receiving a control signal S23, a source that is electrically connected to the input terminal 10 and a drain that is electrically connected to the high voltage output terminal 14. A substrate of the third p-channel transistor is electrically connected to the intersection 20 to provide a voltage V.sub.sub of the intersection 20 to the substrate of the third p-channel transistor 23.
Descriptions will subsequently focus on the operation of the conventional transistor circuitry with reference to FIGS. 2A and 2B. The input terminal receives an electrical signal, a voltage of which is in the range of from the ground potential to the same voltage as the power source voltage V.sub.dd as well as the high voltage V.sub.pp. The charge pump 18 may generate a higher voltage V than the voltage V.sub.dd.
The operations of the transistor circuitry are as follows, assuming that the input terminal receives the electrical signals in the range of from ground to the voltage V.sub.dd. The control signal S21 supplied from the charge pump 18 is at a low level or a ground potential and is applied to the gate electrode of the first n-channel transistor 21 to have the first n-channel transistor 21 turn off. By contrast, the control signal 22 is at a high level or the voltage v.sub.dd and is applied to the gate electrode of the second n-channel transistor 22 to turn it on so that the power source voltage V.sub.dd of the power source voltage terminal 16 is supplied through the second n-channel transistor 22 and the intersection 20 to the substrate of the third p-channel transistor 23. Thus, the substrate voltage V.sub.sub of the third p-channel transistor 23 is held at the same voltage as the power source voltage V.sub.dd. The control signal S23 of the third p-channel transistor 23 is at a high level or the same voltage as the power source voltage V.sub.dd and is applied to the gate electrode of the third p-channel transistor 23 to have the p-channel transistor 23 turn off so that the output voltage OUT14 of the high voltage output terminal 14 is kept at the same voltage as the power source voltage V.sub.dd, while the electrical signals are supplied through the input circuit 11 to the signal output terminal 12 so that a signal output voltage OUT12 appears at the signal output terminal 12 in which a wave form of the output signal OUT12 is analogous to the input signals.
On the other hand, operations of the above transistor circuitry when the input terminal receives the high voltage V.sub.pp are different form those when the input terminal receives the electrical signals.
When the input terminal 10 receives the high constant voltage V.sub.pp, a clock signal CLOCK is supplied to the charge pump 10 in which a voltage of the clock signal is in the range of from the ground potential to the same voltage as the power source voltage. The charge pump that has received the clock signal CLOCK supplies the gate electrode of the first n-channel transistor 21 with a control signal of a higher voltage level V.sub.h than the high voltage V.sub.pp to have the first n-channel transistor 21 turn on so that the high voltage V.sub.pp is supplied to the intersection 20 through the first n-channel transistor 21. By contrast, the control signal S22 that is applied to the gate electrode of the second n-channel transistor 22 switches into a low level or the ground potential to have the second n-channel transistor 22 turn off. As illustrated in FIG. 2B, the voltage level of the control signal applied to the gate of the first n-channel transistor 21 is, however, not rapidly raised up to the higher voltage level V.sub.h. Then, a time T elapses until the turning on of the first n-channel transistor 21 is completed by raising the control signal voltage level S21 over a threshold voltage of the gate electrode of the first n-channel transistor. The substrate voltage V.sub.sub of the third p-channel transistor S23 is not rapidly raised from the power source voltage V.sub.dd up to the high voltage V.sub.pp during the time interval T and thereafter is held at the high voltage V.sub.pp. The control signal S23 to be applied to the gate electrode of the third p-channel transistor S23 switches to a low level of the ground voltage to have the third p-channel transistor S23 turn on so that the high voltage V.sub.pp of the input terminal 10 is supplied through the third p-channel transistor 23 to the high voltage output terminal 14, thereby the output voltage of the high voltage output terminal 14 is not rapidly raised up and held at the high voltage V.sub.pp. The switching on state of the third transistor 23 may prevent the high voltage V.sub.pp from being supplied to the input circuit 11 thereby an intermediate voltage between the ground voltage and the high voltage V.sub.pp appears at the signal output terminal 12.
In view of the circuit design, it is very important to prevent any forward bias between the source and the substrate of any transistors. Namely, it must be prevented that in any transistor an n-type region is applied with a high voltage, while a p-type region is applied with a low voltage. Once any of the transistors is forward biased, a large amount of an electrical current flows through the source region to the substrate thereby a large amount of carriers is injected into the substrate. This may cause an error in operations of the transistor circuits or a latch up. In the above transistor circuitry, the transistor circuits are formed of a p-type semiconductor substrate with an n-type well region in which the p-channel transistor 23 is formed. When the input terminal 10 receives the electrical signals whose voltage level is in the range of form the ground voltage to the same voltage of the power source voltage V.sub.dd, the substrate voltage of the third p-channel transistor 23 is held at the power source voltage V.sub.dd supplied from the power source voltage terminal 16 through the second n-channel transistor 22 in order to prevent a forward bias between the source and substrate of the third p-channel transistor 23. However, the above conventional transistor circuits have the following problems. As described above, the voltage applied to the input terminal 10 is rapidly raised up to the high voltage V.sub.pp from the input signal. Then, the voltage applied to the source of the third p-channel transistor 23 is also rapidly raised up to the high voltage V.sub.pp. Notwithstanding, the substrate voltage of the third p-channel transistor 23 is not rapidly raised up to the high voltage V.sub.pp from the same voltage of the power source voltage V.sub.dd during the time interval T. This is caused by a high internal impedance of the charge pump 18. Such high internal impedance of the charge pump 18 causes a delay in raising the control signal voltage applied to the gate electrode of the first n-channel transistor 21. This delay in raising the control signal voltage S21 causes a delay in the completion of the turning on of the first n-channel transistor 21 thereby the raising of the substrate voltage of the third p-channel transistor 23 is delayed by the time interval T. Then, during the time interval T after the electric signal was changed into the high voltage V.sub.pp, the substrate voltage V.sub.sub of the third p-channel transistor 23 is smaller than the high voltage V.sub.pp applied to the source of the third p-channel transistor 23. This means that the third p-channel transistor 23 is forward-biased between its source and substrate thereby a large amount of carriers is injected into the substrate of the third p-channel transistor 23. Namely, a large amount of the electric current flows through the input terminal 10 to the substrate of the third p-channel transistor 23. This may cause an error in the operation or the latch up thereby resulting in an unoperational state or a broken state of the transistor circuits.
To combat this serious problem, it was proposed to provide a resistance between the input terminal 10 and the third p-channel transistor for suppressing a considerable large amount of the current through the input terminal 10 into the substrate of the third p-channel transistor 23 as illustrated in FIG. 3. This alternative conventional transistor circuitry, however, faces another problem in a voltage drop of the high voltage output terminal 14. When the input terminal receives the high voltage V.sub.pp, the high voltage V.sub.pp is transmitted through the resistor R and the third transistor 23 to the high voltage output terminal 14. The resistor R causes the voltage drop from the high voltage V.sub.pp thereby resulting in a voltage drop of the output voltage at the high voltage output terminal 14. This makes it difficult to fetch a required large amount of the electrical current from the high voltage output terminal 14.
The conventional transistor circuits as illustrated in FIGS. 2A and 3 have a further problem of large power consumption. As described above, the conventional transistor circuitry requires the charge pump 18 to generate the voltage V.sub.h which is higer than the high voltage V.sub.pp to be applied to the gate of the first n-channel transistor 21. For that purpose, the charge pump requires a power for generating the clock signal to be inputted to the charge pump as well as a power to be used for driving the charge pump 18. Those extra powers for the charge pump 18 provides an enlargement of the power consumption. The charge pump further occupies a relatively large area in the transistor circuit. Furthermore, the requirement of the application of the higher voltage V.sub.h to the gate electrode of the first n-channel transistor 21 provides a further requirement for the first n-channel transistor 21 to have a high voltage resistivity. This requires a complicated fabrication process for the transistor circuits.
To settle the above serious problems, it has been required to develop a quite novel transistor circuitry free from any problems as described above.